The product line

Every part, tagged with the truth.

Big tech tells you a product is "real" the moment a slide is rendered. Here, every device carries one of three receipts you can verify today:

SHIPPED — software, runs today DESIGNED — silicon, register-deep VISION — honest looking ahead
Brad Devices product brand hierarchy

The whole brand tree — 6 brands, one fabric. open the 16-page spec ↓

Processors

Two CPU dies, two instruction sets, no ports to write.

Two instructions sets, on purpose. The CPU speaks BradISA; the GPU speaks BradVector. They meet on the BradFusion fabric and share memory (SPMP) — not instructions. Because every Torox GPU die runs that one GPU ISA, a kernel written once decodes identically from integrated to flagship to datacenter. No GPU has to "wait for the CPU world."

BradChip fuses CPU, GPU and NPU on one package with a unified memory pool. BradXon is the flagship processor — its Adaptive Neural Fabric adapts the machine to the workload: compute partitions, a reconfigurable dataflow NPU, and a fabric governor that steers power, clock, and bandwidth. It reallocates budget, not silicon.

  • BradChip GEN 1 · DESIGNED — silicon designed
  • BradXon GEN 1 · DESIGNED — the flagship adaptive processor
  • Two ISAs by design — BradISA (CPU) and BradVector (GPU), never conflated
  • One BradVector GPU ISA across every Torox die — zero porting
Open the BradChip / BradXon spec →
DieRoleStatus
BradChip LiteP2+E4 — integrated SoCDESIGNED
BradChip StandardP4+E4 — everythingDESIGNED
BradChip UltraP6+E4 — performanceDESIGNED
BradChip EliteP8+E4 — proDESIGNED
BradChip MaxP8+E8 — apexDESIGNED
BradXonANF — compute partitions + reconfigurable NPUDESIGNED
The GPU family · Torox

One die name, three jobs.

Every GPU is a Torox die running the same BradVector engine. Your kernel does not care whether it is the integrated BFT, the dedicated BGT, or the datacenter BAT — the ISA is identical.

BradFx GEN 1

BFT100

Integrated GPU. The whole ecosystem's entry graphics — no discrete card needed for the OS to shine.

  • Integrated · one die
  • BradVector engine
  • Ships the same shader math

BradGfx GEN 1

BGT100

Dedicated GPU. For workstations and gamers who want the fabric at full tilt — still one driver, one ISA.

  • Dedicated · discrete
  • BradRT ray-tracing cores on-die
  • 128–512 Neuro-Stream cores

BradApex REFERENCE

BAT100

Datacenter acceleration. The same BradVector ISA as your phone GPU, at rack scale — kernels port with zero changes.

  • Datacenter · scale-out
  • One ISA from mobile to rack
  • Honest: targeted, not fabbed
Memory · BradRAM + SPMP

The end of "VRAM vs the rest."

One unified memory pool. The GPU reads and writes the same fabric the CPU does — zero-copy, no guest in someone else's PCIe lane.

  • SPMP — unified LPDDR, one pool, gigabytes
  • BradRAM — JEDEC LPDDR5X dies + a Brad controller with an L4 SRAM assistant cache
  • Infinity Buffer — the GPU's own on-die SRAM render cache
  • Zero-copy between CPU, GPU and NPU
  • GEN 1 · DESIGNED silicon designed
TierServes
BradRAM L4Controller-die SRAM — AI weights, hot data
SPMPUnified DRAM — everything
Infinity BufferGPU SRAM — render cache
BradSec RAMEncrypted-at-rest memory regions
The fabric · BradFusion

The wire that pretends to be a wall is gone.

BradFusion is the unified fabric that connects processor, GPU, memory and storage as one coherent machine — not a zoo of cables and drivers that refuse to talk to each other.

Software that ships SHIPPED · RUNS TODAY

Every chip's software, done before the chip.

BradOS runs across the whole line. And the shipping software platform — the BradVector toolchain — executes today, in your browser, below. That is what "software before silicon" looks like as a receipt, not a slogan.

Watch the toolchain run See the receipts
Every name, on one map

Ten names. One machine. Zero gloss over.

First visit? This is the whole vocabulary, one row each. Every name carries the same honest footer badge — nothing here is a slide. Names you met in Parts 01–05, now standing next to each other so they read as parts, not noise.

NameIs what sits inReceiptGo verify →
BradChip the CPU die — P/E cores + NPU DESIGNED die map
BradXon flagship — ANF partitions, reconfigurable NPU, governor GEN 1 · DESIGNED one fabric, one flagship
BradVector / BVRT the GPU's ISA + the runtime that executes it SHIPPED runs in this tab
Torox one die, three jobs — BFT / BGT / BAT DESIGNED Torox GPU family
BGT100 die: BradGfx — the dedicated BradVector GPU DESIGNED PART 02
BFT100 die: BradFx — the integrated BradVector GPU DESIGNED PART 02
BAT100 die: BradApex, datacenter DESIGNED PART 02
SPMP the unified DRAM pool DESIGNED PART 03
BradRAM JEDEC LPDDR5X dies + a Brad controller: DDS prefetch, L4 SRAM cache, inline encryption DESIGNED PART 03
BradFusion Fabric the fabric die — die-to-die + chip-link DESIGNED PART 04
BradOS runs across every tier, Mobile → Compute DESIGNED OS section
BradVector die: BGT/BFT/BAT the GPU silicon — recompute that IS the fabric DESIGNED Torox table
Kinetic Unified Driver one driver that rules CPU/GPU/NPU — targets Vulkan 1.4, DX12, Metal 3, SYCL 2020 DESIGNED OS section

SHIPPED = software that ships today · DESIGNED = silicon with a receipt wherever it's claimed · VISION = honest, not yet real

The parts fuse into one machine.

See how every product here plugs into the same fabric.

The whole ecosystem →